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@@ -15,7 +15,7 @@
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Name: iverilog
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Version: 0.9.7
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-Release: 2%{?_dist_release}
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+Release: 3%{?_dist_release}
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Summary: A Verilog simulation and synthesis tool
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Group: Applications/Engineering
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@@ -108,6 +108,9 @@ rm -rf %{buildroot}
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%changelog
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+* Thu Sep 01 2016 Toshiaki Ara <ara_t@384.jp> - 0.9.7-3
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+- rebuild with gcc-5.4.0
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+
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* Sun Apr 5 2015 Ryoichi INAGAKI <ryo1@toki.waseda.jp> - 0.9.7-2
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- rebuilt with readline 6.3
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